Multiple Voltage Partitioning Techniques of VLSI

Author:

Daniel Hsu

Mentor:

Ching-hwa Cheng, Associate Professor of Electronic Engineering, Feng Chia University

Duel voltage techniques in very large scale integrated circuit (VLSI) power optimization are currently one of the most promising ways to achieve low power consumption. Circuits are typically driven with a single supply voltage, but it is possible to use two different voltages to drive circuits. The portion of circuits driven with lower voltage allows for reduced power consumption but also creates performance degradation in terms of delay in the overall chip. Changes in area can also be expected when the circuit is split into two domains. To overcome this problem we designed and implemented a bin packing technique to maximize power savings while balancing the increases in delay and area. To optimize the two voltage domain circuit, each property (power, delay, area) of circuit modules in the chip is analyzed independently by applying a bin packing algorithm to see which modules should be placed into the low voltage domain. The power bin packing is determined by the maximum power consumption reduction. The delay and area bin packing is determined by how much of an increase in overall delay and area is tolerable compared to the original overall chip delay and area. The circuit modules in the intersection of these three bins are identified and placed into the low voltage domain, while the remaining modules are left in the original (high) voltage. A video encoder test chip is used to validate effectiveness of our proposed method, and design simulation results show that power consumption drops by 60% with only a 20% increase in delay times. Compared to this chip’s original single voltage design results, these values demonstrate a favorable trade-off.


Presented by:

Daniel Hsu

Date:

Saturday, November 23, 2013

Time:

9:55 AM — 10:10 AM

Room:

Science 116 (Physics Lab)

Presentation Type:

Oral Presentation

Discipline:

Engineering